At a high-performance computing event this month AMD has given a little more detail about the 3D chip-stacking techniques it’s looking at to mitigate the slowing of Moore’s Law. The multi-chip, or chiplet architecture that’s propping up the AMD Ryzen 3000 processors launching this year looks to only be a step on the road towards fully 3D stacked, heterogeneous processor designs.

With the performance benefits of process node shrinks weakening with every new lithography AMD is keenly looking for ways to keep its products moving forward. While the new Zen 2 chiplet design is an important technique for increasing the amount of silicon in a single socket, it’s a trick that’s going to lose its lustre fast.

“That technique of putting more and dies is going to run out pretty quick,” says Forrest Norrod, senior vice president and GM of AMD’s datacentre group, “because there’s a physical limit to how many die you can put into a given socket area. We’re already at the point where today’s CPUs, the packages, are pretty darned close to the size of the original iPhone. They’re huge. You can’t get any more area in two dimensions, so what do you have to do? You go up.”